High-Rate Viterbi Processor: A Systolic Array Solution

In exploiting the potentials of highly parallel architectures to speed up the computation rate of systems enabled by VLSI, special attention has to be paid to designing algorithms such that they can be mapped onto parallel hardware. The main part of the Viterbi algorithm (VA) is a nonlinear feedback loop, the ACS recursion (add-compare-select recursion), which presents a bottleneck for high-speed implementations and cannot be circumvented by standard means. By identifying that the two operations of the loop form an algebraic structure called serniring, we show that the ACS recursion of the Viterbi algorithm can be written as a linear vector recursion. This allows us to employ the powerful techniques of parallel processing and pipelining, known for conventional linear systems, to achieve high throughput rates. Since the VA can be written as a linear vector recursion, it can be implemented by systolic arrays. For the class of shuffle exchange codes to be decoded by the Viterbi algorithm, hardware efficient code-optimized arrays are presented. In addition, it is shown that carry-save arithmetic can be used for the operations of ACS recursion, allowing each word-level operation to be pipelined and carried out by an efficient bit-level systolic array.